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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:22:51 03/03/2012 
-- Design Name: 
-- Module Name:    RA - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity IR is
		Port ( ir_out : out  STD_LOGIC_VECTOR (17 downto 0);
           inst_word_i : in  STD_LOGIC_VECTOR (17 downto 0);
			  ir_sel: in STD_LOGIC;
           clk : in  STD_LOGIC);
end IR;

architecture Behavioral of IR is
begin
	process(ir_sel)
	begin
		--if(rising_edge(clk)) then
			if ir_sel = '1' then 
				ir_out <= inst_word_i;
		--	end if;
		end if;
	end process;
end Behavioral;